US EditionR&D: Compact Modeling of Trap-Assisted Tunneling Current in 3-D NAND Flash Memory
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R&D: Compact Modeling of Trap-Assisted Tunneling Current in 3-D NAND Flash Memory
IEEE Transactions on Electron Devices has published an article written by Hyungjun Jo, Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, and Hyungcheol Shin, Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, and Integra Semiconductor Ltd, Seoul, South Korea…
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