China's CXMT Says New Memory-Chip Platform Enters Mass Production
- On Sunday, Chinese DRAM chipmaker CXMT announced its fifth-generation technology platform entered mass production, positioning the firm to compete with Samsung Electronics, SK Hynix, and Micron Technology in the global memory chip market.
- Beijing seeks to reduce dependence on foreign semiconductor technology; export controls since 2022 have restricted China's access to advanced chipmaking equipment and software, spurring local firms like CXMT to develop independent solutions.
- Using 'quadruple patterning,' the Hefei-based company reduced feature spacing to 11.95 nanometres, enabling 50 per cent more data capacity and 50 per cent more gross chip dies per wafer than its fourth-generation platform.
- At the 2026 World Manufacturing Convention in Hefei, CXMT Vice President Luo Xiaodong claimed the firm's process capability is "now on par with the most advanced mass-produced nodes out there in the industry."
- CXMT also unveiled two 24-gigabit LPDDR5X products for smartphones and portable devices. Listed on Shanghai's STAR Market this year, the company aims to provide electronics manufacturers an additional supply source in the global memory chip market.
39 Articles
39 Articles
CXMT announces mass production of fifth-generation DRAM platform · TechNode
CXMT announced mass production of its fifth-generation DRAM technology platform, known as the G5 Platform, at the 2026 World Manufacturing Convention in Hefei on Sept. 20. The company also unveiled a new LPDDR5X product lineup based on the platform. The G5 Platform uses quadruple patterning to achieve an 11.95-nanometer active-area half-pitch for memory arrays. CXMT […]
Reuters reported on the 20th (local time) that China's Changxin Technology (CXMT) has begun mass production of its 5th-generation DRAM process. According to the report, CXMT's 5th-generation platform is designed to produce high-performance memory semiconductors at lower costs and with lower power consumption. CXMT stated that it has reduced the spacing between key structures of the memory array, which stores data on the chip, to the 11.95 nanome…
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