US EditionSK Hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025
- SK hynix unveiled a new 30-year roadmap for DRAM technology during the IEEE VLSI Symposium taking place in Kyoto, Japan, from June 8 to 12, 2025.
- The company announced this strategy to address scaling limitations faced by current DRAM platforms and to sustain long-term innovation.
- CTO Cha Seon Yong delivered a plenary on June 10 titled "Driving Innovation in DRAM Technology," highlighting 3D DRAM and the 4F Vertical Gate platform as future pillars.
- He noted that prior to 2010, it was anticipated that DRAM development would encounter challenges at the 20-nanometer scale, but ongoing technological progress has allowed significant advancements beyond that threshold, and he highlighted addressing rising costs through continuous innovation.
- On the event's last day, Vice President Joodong Park will present research on how Vertical Gate and wafer bonding technologies affect DRAM electrical characteristics, supporting SK hynix’s roadmap goals.
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SK hynix participates in IEEE VLSI symposium 2025 in Kyoto, Japan June 8-12
IEEE VLSI 2025: SK hynix Presents Future DRAM Technology Roadmap
SK hynix Inc. announced that it presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 2025 (*) held in Kyoto, Japan. Cha Seon Yong, CTO, SK hynix, delivered on June 10th a plenary session on Driving Innovation in DRAM Technology: Towards […] The post IEEE VLSI 2025: SK hynix Presents Future DRAM Technology Roadmap appeared first on StorageNewsletter.
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