Optimizing Analog With Layout In The Loop

Optimizing Analog With Layout In The Loop

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly optimized schematic often achieves significantly degraded…