Multicore and Worst-Case Execution Time (WCET) support for RISC-V

Alibaba unveils server-grade, high-performance RISC-V chip

#thenewscompany :  Alibaba Group’s research division, Damo Academy, has unveiled its first server-grade processor based on the open-source RISC-V architecture. This marks a significant step in China’s push for semiconductor self-reliance. The C930 high-performance computing chip will begin shipping in March as part of Alibaba’s broader strategy to expand its artificial intelligence (AI) and cloud computing capabilities. According to Alibaba, the…

Multicore and Worst-Case Execution Time (WCET) support for RISC-V

LDRA in the UK has added support for multicore processors using the RISC-V open instruction set architecture with worst case execution time (WCET) analysis to its tool suite. A module automatically analyse shared memory, cache resource access, coherency issues, and measures worst case execution time to guarantee deterministic execution time for RISC-V processors that use […] The post Multicore and Worst-Case Execution Time (WCET) support for RIS…