JEDEC SPHBM4 New Standard to Deliver HBM4-Level Throughput with Reduced Pin Count

JEDEC SPHBM4 New Standard to Deliver HBM4-Level Throughput with Reduced Pin Count

JEDEC Solid State Technology Association announced it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 devices are similar to the HBM4 devices commonly used in AI accelerators, using the same DRAM dies on a new interface base die which can be mounted on standard organic substrates. In contrast, […] The post JEDEC SPHBM4 New Standard to Deliver HBM4-Level Throughput with Reduced Pin Count appeare…

JEDEC developing reduced pin count HBM4 standard to enable higher capacity

The JEDEC Solid State Technology Association is developing a way to increase overall high bandwidth memory (HBM) capacity with longer channel distances to enable more HBM stacks per GPU. JEDEC is the Joint Electron Device Engineering Council. Standard Package High Bandwidth Memory (SPHBM4) is similar to an HBM4 device with its silicon substrate, but with […]