Intel Demos Cellphone-Size Multi-Chiplet AI Package 12x Larger Than TSMC's Biggest, with HBM5, 14A Compute Tiles and 18A SRAM

Intel Demos Cellphone-Size Multi-Chiplet AI Package 12x Larger Than TSMC's Biggest, with HBM5, 14A Compute Tiles and 18A SRAM

Intel Demos Cellphone-Size Multi‑Chiplet AI Package 12× Larger Than TSMC’s Biggest? What HBM5, 14A Compute Tiles, and 18A SRAM Really Mean Intel has unveiled a concept multi‑chiplet AI package roughly the size of a modern smartphone, integrating future HBM5 stacks, 14A compute tiles, and 18A SRAM cache tiles on a next‑gen glass substrate with EMIB and Foveros Direct. Here’s what was shown, what’s likely, and why it matters for data centre AI. I…