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Failure Analysis HW Enables System-Level Debug For 3D ICs (Google, TU Delft)
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Failure Analysis HW Enables System-Level Debug For 3D ICs (Google, TU Delft)
Researchers from Google and Delft University of Technology published a technical paper titled “Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs.” Abstract Excerpt: “This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing …
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