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Published 22 days ago

TSMC lays out roadmap for massive, kilowatt-class chip packages and terabit optical links

Summary by Tech Spot

Starting with the chip packaging tech, which TSMC has branded "CoWoS" (Chip-on-Wafer-on-Substrate), it's essentially an enhanced version of typical chiplet designs, where multiple smaller dies are integrated together into one package. But TSMC is taking it to incredible new levels of scale and complexity.Read Entire Article

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TSMC lays out roadmap for massive, kilowatt-class chip packages and terabit optical links

Starting with the chip packaging tech, which TSMC has branded "CoWoS" (Chip-on-Wafer-on-Substrate), it's essentially an enhanced version of typical chiplet designs, where multiple smaller dies are integrated together into one package. But TSMC is taking it to incredible new levels of scale and complexity.Read Entire Article

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